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| Direct Conversion IC for Digital Satellite Broadcast Tuner CXA3685ER Description The CXA3685ER is an IC developed for direct orthogonal detection of L band (1 to 2GHz) IF signals in a digital satellite broadcast reception tuner. This direct conversion (Zero-IF) technology eliminates the need for the SAW filter that was formerly necessary. In addition, the CXA3685ER incorporates an RF gain control amplifier, oscillator circuit, wide-band phase shifter circuit and other RF circuits, a baseband LPF, baseband gain control amplifier, tuning PLL, and the inductor and varactor diode needed for a tuning VCO. This makes it possible to realize the front-end RF block without tuning the RF circuits. (Applications: BS/CS digital broadcast (ISDB-S) tuner) Features Low power consumption: 430mW (typ.) No need for an external inductor and varactor diode 3.3V single power supply Reception frequency: 950MHz to 2150MHz Wide input range (typ. -65dBm to -15dBm) Internal wide band 90 phase shifter Internal output for controlling an external attenuator Reference signal output for the demodulation circuit Enables to use external reference signals Small package: 48-pin VQFN Enables to reduce power consumption in power save mode when not used: 180mW (typ.) Package 48-pin VQFN (Plastic) Note) This IC has pins whose electrostatic discharge strength is weak as the high-frequency process is used. Take care of handling the IC. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E06X01-CR CXA3685ER Absolute Maximum Ratings Supply voltage Storage temperature AVCC, REFVCC, DVCC, OSCVCC, RFVCC Tstg -0.3 to +3.6 -55 to +150 V C (Ta = 25C) Operating Conditions Supply voltage Operating temperature AVCC, REFVCC, DVCC, OSCVCC, RFVCC Topr 3.15 to 3.45 -10 to +70 V C Outline Specifications Structure Reception frequency Reception bandwidth IF output level Crystal oscilaltor frequency PLL control Supply voltage Power consumption in power save mode Direct conversion 950MHz to 2150MHz 22.5MHz 0.7Vp-p 4MHz to 32MHz I2C bus 3.15V to 3.45V 430mW (typ.) 180mW (typ.) -2- CXA3685ER Block Diagram and Pin Configuration 35 OSCGND 29 REFGND 30 REFVCC 27 REFIN 32 DGND 31 DVCC 26 XTO 34 ABS 28 XTI OSCREG 37 OSCVCC 38 TEST_EN 39 TEST_CL 40 1/2 TEST_DA 41 Phase Shifter DCAMP ISOGND 43 RFAGC RFGND 44 LPF LPF Baseband AGC VCO 1/2 PLL REF OSC I2C BUS 25 NC 33 CP 36 VT 24 REFOUT 23 ADR 22 SCL 21 SDA 20 DGND2 TEST_VF 42 19 PLLREG 18 AGND 17 IOUT RFINX 45 16 OFFSET_I RFIN 46 15 OFFSET_Q RFVCC 47 EA EAOUT 48 RA MA x1.125 AGC 14 QOUT 13 AGND AVCC 10 LD 11 EACONT RACONT MAOUT MACONT RAOUT AGND PORT AGC -3- REFCLOCK NC 12 1 2 3 4 5 6 7 8 9 CXA3685ER Pin Description and Input/Output Pin Equivalent Circuit Pin No. Symbol Pin voltage [V] RFVCC 47 Equivalent circuit Description 10k 1 EACONT 2.7 1 48 Gain control for an external attenuator circuit. (This pin voltage depends on the AGC voltage. This is an example of 3.3V.) (See page 18.) 1k 44 RFGND RFVCC 47 2 PORT 0 or 3.2 2 Port output 44 RFGND RFVCC 3 RAOUT 3.2 47 10k 4 290k 3 Gain control for the RFAGC circuit. (This pin voltage depends on the AGC voltage. This is an example of 3.3V.) (See page 18.) 4 RACONT 3.0 44 RFGND 1k 110k AVCC 10 5 MAOUT 3.3 10k 6 70k 1k 5 Gain control for the DCAMP circuit. (This pin voltage depends on the AGC voltage. This is an example of 3.3V.) (See page 18.) 6 MACONT 1.7 8 13 18 AGND 35k -4- CXA3685ER Pin No. Symbol Pin voltage [V] Equivalent circuit AVCC 10 1k 500 7 4k 8 13 18 AGND 1k 1k Description 7 AGC 0 to 3.3 AGC control voltage input 8, 13, 18 AGND 0 GND for the mixer and baseband circuit DVCC 31 140k 9 REFCLOCK -- 500 9 5k Frequency change for the reference signal output (See page 19.) 45k 32 DGND 10 AVCC 3.3 Power supply for the mixer and baseband circuit DVCC 31 11 LD 0 or 3.3 11 PLL lock detection 32 DGND 12 NC -- Not used 14 QOUT 1.6 AVCC 10 10k 17 14 2k Baseband signal output 17 IOUT 1.6 18 13 8 AGND -5- CXA3685ER Pin No. Symbol Pin voltage [V] Equivalent circuit AVCC Description 15 OFFSET_Q 2.2 10 33 16 15 DC offset correction output for the baseband circuit 16 OFFSET_I 2.2 18 13 8 AGND DVCC 31 19 PLLREG 2.6 19 Reference voltage output for a PLL circuit 32 DGND 20 DGND2 0 DVCC 31 10k 20 5k 21 GND for the ACK circuit 21 SDA 0 or 3.3 Data input 32 20 DGND DGND2 DVCC 31 10k 22 SCL 0 or 3.3 5k 22 Clock input 32 DGND -6- CXA3685ER Pin No. Symbol Pin voltage [V] DVCC 31 Equivalent circuit Description 140k 23 ADR 0 5k 23 5k Address select 45k 32 DGND DVCC 31 24 REFOUT 2.0 or 2.5 24 Reference signal output 32 DGND 25 NC -- REFVCC 30 Not used 26 XTO 2.4 26 Crystal oscillator connection for reference signal oscillation 29 REFGND REFVCC 30 100k 27 REFIN 0 27 100k External reference signal input 29 REFGND -7- CXA3685ER Pin No. Symbol Pin voltage [V] Equivalent circuit REFVCC 30 Description 28 XTI 2.6 28 30k Crystal oscillator connection for reference signal oscillation 29 REFGND 29 30 31 32 REFGND REFVCC DVCC DGND 0 3.3 3.3 0 DVCC 31 GND for the REFOSC block Power supply for the REFOSC block PLL Power supply PLL GND 33 CP -- 500 33 Charge pump output for tuning PLL 32 DGND DVCC 31 34 ABS -- 500 34 3k Auto band select input 32 DGND 35 OSCGND 0 OSCVCC 38 oscillator GND 37 10k 36 VT -- 36 Control voltage for tuning PLL 35 OSCGND -8- CXA3685ER Pin No. Symbol Pin voltage [V] Equivalent circuit OSCVCC 38 Description 37 OSCREG 2.6 37 Regulator output for an oscillator 35 OSCGND 38 39 OSCVCC TEST_EN 3.3 -- DVCC 31 Power supply for an oscillator Test enable 39 1k 40 TEST_CL -- 40 41 32 Test clock input DGND 41 42 43 44 TEST_DA TEST_VF ISOGND RFGND -- -- 0 0 43 Test data input ISOGND Test power supply Isolation GND GND for the RF block RFVCC 47 45 RFINX 1.4 2.1k 45 2.1k 46 RF input 46 RFIN 1.4 44 RFGND 1.07k 47 RFVCC 3.3 RFVCC 47 Power supply for the RF block 10k 48 EAOUT 3.3 1 48 Gain control for an external attenuator circuit 1k 44 RFGND -9- CXA3685ER Electrical Characteristics (See the Electrical Characteristics Measurement Circuit.) VCC = 3.3V, Ta = 25C Item Symbol REFICC DICC Circuit current OSCICC AICC RFICC Input level range IQ phase error IQ amplitude error LPF cutoff frequency Noise figure OSC phase noise RF pin leakage RFDR EPH EAMP FC NF PN LO RF = 950MHz AGC voltage = 3.3V fIF = 10MHz RF = 2150MHz 100kHz offset 50 termination, AGC voltage = 3.3V -78 -50 AGC voltage = 3.3V IQ output = 0.7Vp-p/1k load Measurement conditions Min. 1 7 8 40 10 -65 -5 -2 19 1.5 0.5 22.5 10 -82 -60 Typ. 3 14 18 71 18 Max. 5 21 28 100 26 -15 7 2 26 15 Unit mA mA mA mA mA dBm deg dB MHz dB dBc/Hz dBm PLL Block Item SCL and SDA input High level input voltage Low level input voltage High level input current Low level input current CPO (Charge pump) Output current 1 Output current 2 Output current 3 Output current 4 Output current 5 Output current 6 Output current 7 Output current 8 REFOSC Oscillation frequency range REFOUT output level PORT output voltage EAOUT output voltage FXTOSC REFOUT No load, 4MHz output PORTV ON, 1k load EAOUTV Max. Gain, 350 load 4 0.2 3 2.7 0.5 3.2 3 32 0.8 3.3 3.3 MHz Vp-p V V ICPO1 ICPO2 ICPO3 ICPO4 ICPO5 ICPO6 ICPO7 ICPO8 when 100A is selected when 150A is selected when 200A is selected when 300A is selected when 500A is selected when 1000A is selected when 1500A is selected when 2000A is selected 50 75 100 150 250 100 150 200 300 500 150 225 300 450 750 A A A A A A A A VIH VIL IIH IIL VIH = VCC VIL = GND -30 2.3 GND 0 -20 3.3 1 1 V V A A Symbol Measurement conditions Min. Typ. Max. Unit 500 1000 1500 750 1500 2250 1000 2000 3000 - 10 - CXA3685ER Register Block Item Bus timing (I2C bus) SCL clock frequency Bus free time between "STOP" condition and "STOP" condition Start-Hold time Low hold time High hold time Start-Setup time Data-Hold time Data-Setup time Rise time Fall time Stop-Setup time Capacitive load of bus line fSCL tBUF tH; STA tLOW tHIGH tS; STA tH; DAT tS; DAT tR tF tS; STO Cb 600 400 0 1300 600 1300 600 600 0 100 300 300 900 400 kHz ns ns ns ns ns ns ns ns ns ns pF Symbol Measurement conditions Min. Typ. Max. Unit I2C Bus Timing Chart tBUF SDA tR tF tS; STO tS; STA SCL tH; STA START tLOW tHIGH tS; DAT tH; DAT STOP CLOCK DATA CHANGE tS; DAT= Data setup time tH; DAT= Data hold time tS; STO= Stop setup time tR= Rise time tF= Fall time tBUF= Bus free time tW; STA= Start waiting time tH; STA= Start hold time tLOW= Low clock pulse width tHIGH= High clock pulse width - 11 - CXA3685ER Electrical Characteristics Measurement Circuit 3.3V 3.3V 15p 1000p 0.68 1000p 1000p 10 56k 3.3k NeoCapacitor: PSLA0J226M VT 36 OSCGND 35 ABS 34 68k 16MHz X'tal CP 33 DGND 32 DVCC 31 10 REFVCC 30 REFGND 29 XTI 28 REFIN 27 XTO 26 15p REFOUT 24 1 ADR 23 1000p 37 OSCREG NeoCapacitor 22 1000p 38 OSCVCC 39 TEST_EN 10 40 TEST_CL 41 TEST_DA NC 25 REFOUT 3.3V SCL 22 200 27p SDA 21 200 DGND2 20 27p 10 SCL I2C BUS SDA 42 TEST_VF PLLREG 19 1000p 43 ISOGND AGND 18 44 RFGND IOUT 17 1 1k IOUT 45 RFINX 47p RFIN 3.3V 47p 100p 47 RFVCC 46 RFIN OFFSET_I 16 0.1 OFFSET_Q 15 QOUT 14 0.1 QOUT 1 1k 9 REFCLOCK 8 AGND 2 PORT 10 10 AVCC 7 AGC 48 EAOUT 6 MACONT 4 RACONT EACONT 5 MAOUT AGND 13 3 RAOUT 1000p 1k 10k 10 1 10 - 12 - LOCK_DET PORT AGCIN 3.3V 12 NC 11 LD 1 CXA3685ER Description of Operation Control Registers Most of the functions of this IC can be programmed and controlled by the control registers. I2C Bus Control The various registers are controlled by setting values in the internal control registers via the serial interface which is comprised of the two pins SDA (Pin 21) and SCL (Pin 22). This IC supports the Write mode for receiving various data, and the Read mode for transmitting various data. The mode is set by S0 (R/W bit). The Write mode for receiving various data is set when the R/W bit is "0", and the Read mode for transmitting various data is set when the R/W bit is "1". S7 Slave Address 1 S6 1 S5 0 S4 0 S3 0 S2 MA1 S1 MA0 S0 R/W Four different slave addresses (IC addresses) can be set by externally setting the ADR pin (Pin 23) to specific voltages so that multiple PLL can exist within a single system. ADR pin voltage Slave Address 0 to 0.1VCC (Default) 1100 000R/W Open or 0.2 to 0.3VCC 1100 001R/W 0.4 to 0.6VCC 1100 010R/W 0.9 to VCC 1100 011R/W Note) When leaving the ADR pin (Pin 23) open, always connect a capacitor of approximately 1000pF to the ADR pin. The 8-bit slave address (IC address), 8-bit sub address, and a number of 8-bit data strings are input MSB first in series to the SDA pin. An ACK is returned to confirm that the data was accepted each time 8 bits of data are input to the SDA pin. To set the data for only a specific separate sub address, either send the Stop condition and then reset the sub address, or send the data continuously including the data portions that are not to be changed. Only the auto increment mode is supported, and modes that specify only specific sub addresses in the manner of "sub address + data + sub address + data" are not supported. SDA S7 S6 S5 S4 S3 S2 S1 S0 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK Slave Address Sub Address Data Data SCL Start Condition Stop Condition Start Condition The Start condition is established when the signal input to the SDA pin falls while the SCL pin is High level. Stop Condition The Stop condition is established when the signal input to the SDA pin rises while the SCL pin is High level. - 13 - CXA3685ER Description of the Setting in Write Mode The CXA3685ER enables to write data to registers when the R/W bit is set to "0". Input clock to the SCL pin. The SDA pin data is written to registers at the rising edge of the clock. Bit name Register name Sub Address Byte0 Byte1 Byte2 Byte3 Byte4 Byte5 Byte6 Byte7 Byte8 Byte9 Byte10 Byte11 00 01 02 03 04 05 06 07 08 09 0A 0B Bit7 M11 M3 M12 PS8 PS9 EA_7 MA_7 RA_7 0 0 0 Bit6 M10 M2 BAND2 PS7 R2 EA_6 MA_6 RA_6 0 0 0 Bit5 M9 M1 PS6 R1 EA_5 MA_5 RA_5 0 0 0 0 Bit4 M8 M0 PS5 R0 EA_4 MA_4 RA_4 0 0 0 0 Bit3 M7 S3 C2 PS4 REFOUT EA_3 MA_3 RA_3 1 0 0 0 Bit2 M6 S2 C1 PS3 0 Bit1 M5 S1 C0 PS2 0 Bit0 M4 S0 PORT PS1 0 Ack A A A A A A A A A A A A BAND1 BAND0 EA_2 EA_1 EA_0 MA_2 MA_1 MA_0 RA_2 RA_1 RA_0 0 0 0 0 0 0 0 0 0 0 0 0 REFOSC1 REFOSC0 A M12 to M0 S3 to S0 BAND2 to BAND0 C2 to C0 PORT PS9 to PS1 R2 to R0 REFOUT EA_7 to EA_0 MA_7 to MA_0 RA_7 to RA_0 REFOSC1 to REFOSC0 : Acknowledge bit : Main counter : Swallow counter : VCO band selection : Charge pump current setting : Port output setting : Power save mode setting : Number of frequency divisions for reference counter setting : REFOUT pin output setting : EAOUT output adjustment : MAOUT output adjustment : RAOUT output adjustment : Crystal oscillator-Oscillation amplitude switching - 14 - CXA3685ER Main Counter and Swallow Counter Setting Main Counter (M0 to M12), Swallow Counter (S0 to S3) The VCO tuning frequency is obtained by the following formula. RF = (1/2) x fosc = fref x (16M + S) RF fosc fref M S : Tuning frequency : Local oscillator circuit frequency : Comparison frequency : Main counter frequency division ratio : Swallow counter frequency division ratio The variable frequency division ranges of M and S are as follows, and are set as binary. S < M 8191 0 < S 15 VCO Band Selection VCO consists of 6 bands and 8 sub bands in each band. Band data is required to be input according to each oscillation frequency. Sub bands are automatically set when the band is set. VCO oscillation frequency vs. Vt voltage Band1 Vt voltage Band2 Band6 Sub band 1 to 8 Oscillation frequency - 15 - CXA3685ER VCO Band Setting BAND2 0 0 0 0 1 1 BAND1 0 0 1 1 0 0 BAND0 0 1 0 1 0 1 VCO band setting Band1 Band2 Band3 Band4 Band5 Band6 Reception frequency 950MHz Band1 1125MHz 1125MHz < Band2 1350MHz 1350MHz < Band3 1625MHz 1625MHz < Band4 1875MHz 1875MHz < Band5 2050MHz 2050MHz < Band6 2150MHz Charge Pump Current Setting C2 0 0 0 0 1 1 1 1 C1 0 0 1 1 0 0 1 1 C0 0 1 0 1 0 1 0 1 Output current [A] 100 200 300 400 500 1000 1500 2000 Port Output Setting PORT 0 1 Output Low High Power Save Mode Setting The CXA3685ER can be set to power save mode by registers (reduction of power consumption when not using the IC). Operate the following bits simultaneously in power save mode. Sets PS9 to PS1 to High - 16 - CXA3685ER Number of Frequency Divisions for Reference Counter Setting R2 0 0 0 0 1 1 1 1 R1 0 0 1 1 0 0 1 1 R0 0 1 0 1 0 1 0 1 Number of frequency divisions 2 4 8 16 32 64 128 256 REFOUT Output Setting REFOUT 0 1 Output ON OFF Crystal Oscillator - Amplitude Switching Setting REFOSC1 0 0 1 1 REFOSC0 0 1 0 1 Oscillation amplitude Large Middle Small Ultra small REFIN Pin Connect the REFIN pin to GND when using the internal REFOSC circuit by connecting a crystal oscillator. Input signal to the REFIN pin at CMOS level (3.3Vp-p) when using an external reference signal. - 17 - CXA3685ER AGC Control Circuit Setting Method This IC incorporates a circuit for controlling an external ATT circuit (EA), a circuit for controlling RFAGC (RA) and a circuit for controlling DCAMP (MA). The internal equivalent circuit for each circuit is an operational amplifier as shown bellow. The characteristics of each amplifier can be controlled by setting an external resistance, or current and internal resistance. AGC voltage OUT R1 = 10k R1 SW1 R2 SW2 CONT Current setting Turn off both SW1 and SW2 when using an external resistor. Turn on both SW1 and SW2 when using the internal resistor. SW1 Setting EA, MA, RA_0 0 1 SW1 OFF ON SW2 Setting EA, MA, RA_4 0 1 SW2 OFF ON Current Setting EA, MA, RA_3 0 0 0 0 1 1 1 1 EA, MA, RA_2 0 0 1 1 0 0 1 1 EA, MA, RA_1 0 1 0 1 0 1 0 1 Current value [A] 25 50 75 100 125 150 175 200 Resistance Value (R2) Setting EA, RA, MA_7 0 0 0 0 1 1 1 1 EA, MA, RA_6 0 0 1 1 0 0 1 1 EA, MA, RA_5 0 1 0 1 0 1 0 1 Resistance value [] 40k 35k 30k 25k 20k 15k 10k 5k Set the current and R2 to the following values to realize the AGC control characteristics (data on page 21) in the Electrical Characteristics Measurement Circuit. EA : Current value = 75A, R2 = 40k MA : Current value = 200A, R2 = 40k RA : Current value = 50A, R2 = 10k - 18 - CXA3685ER REFOUT Frequency The REFOUT pin outputs the signal which frequency is divided from the reference signal by changing the voltage of Pin 9. Voltage of Pin 9 0 to 0.1VCC 0.2 to 0.3VCC 0.4 to 0.6VCC 0.9 to VCC Frequency division ratio 1 2 8 4 Example Voltage of Pin 9 (when VCC = 3.3V) [V] 0 to 0.33 0.66 to 0.99 1.33 to 1.98 2.97 to 3.3 Crystal oscillator frequency [MHz] 4 8 32 16 REFOUT output frequency [MHz] 4 4 4 4 Description of the Setting in Read Mode When the R/W bit is set to "1", the 8-bit data written to registers can be read. This IC can read the PLL locked or unlocked status and VCO sub band setting. The read data formats are as follows. bit7 Slave Address 1 D7 Status Byte FL bit6 1 D6 0 bit5 0 D5 bit4 0 D4 bit3 0 D3 bit2 MA1 D2 0 bit1 MA0 D1 0 bit0 1 D0 0 Ack A Ack A SBAND2 SBAND1 SBAND0 MA0 to MA1 : Slave address FL : PLL lock detection (0: Unlocked, 1: Locked) SBAND2 to SBAND0 : Sub band detection SBAND2 0 0 0 0 1 1 1 1 SBAND1 0 0 1 1 0 0 1 1 SBAND0 0 1 0 1 0 1 0 1 VCO sub band setting Sub Band1 Sub Band2 Sub Band3 Sub Band4 Sub Band5 Sub Band6 Sub Band7 Sub Band8 - 19 - CXA3685ER Measurement Conditions for Representative Characteristics Supply voltage: 3.3 [V] AGC voltage : 0 to 3.3 [V] I2C Bus Register Conditions Register name Byte0 Byte1 Byte2 Byte3 Byte4 Byte5 Byte6 Byte7 Byte8 Byte9 Byte10 Byte11 Bit name Sub Address 00 01 02 03 04 05 06 07 08 09 0A 0B M11 M3 M12 0 0 0 0 1 0 0 0 0 M10 M2 BAND2 0 0 0 0 1 0 0 0 0 M9 M1 BAND1 0 1 0 0 0 0 0 0 0 M8 M0 BAND0 0 1 1 1 1 0 0 0 0 M7 S3 1 0 0 0 1 0 1 0 0 0 M6 S2 0 0 0 1 1 0 0 0 0 0 M5 S1 0 0 0 0 1 1 1 0 0 0 M4 S0 0 0 0 1 1 1 0 0 0 0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Ack A A A A A A A A A A A A - 20 - CXA3685ER Representative Characteristics Input Sensitivity AGC voltage: 3.3V IQ output: 0.7Vp-p -90 -85 30 25 Noise Figure AGC voltage: 3.3V RF input level [dBm] -80 -75 -70 -65 -60 700 900 1100 1300 1500 1700 1900 2100 2300 2500 RF frequency [MHz] 10 5 700 900 1100 1300 1500 1700 1900 2100 2300 2500 RF frequency [MHz] NF [dB] 20 15 AGC Control Characteristic 100 90 80 70 60 50 40 30 20 10 0 -10 -20 -30 -40 -50 -60 -70 Baseband LPF Frequency Response RF: 1318MHz 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 1 10 Output frequency [MHz] RF: 1318MHz RF input level: -40dBm Output level [dBm] Gain [dB] 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 100 AGC [V] Phase Error IQ output: 0.7Vp-p 5 4 2 1 0 -1 -2 -3 -4 -5 1.00 0.80 Amplitude Error IQ output: 0.7Vp-p Amplitude error [dB] RF frequency [MHz] 3 0.60 0.40 0.20 0.00 -0.20 -0.40 -0.60 -0.80 -1.00 Phase error [deg] 800 1000 1200 1400 1600 1800 2000 2200 2400 700 900 1100 1300 1500 1700 1900 2100 2300 2500 RF frequency [MHz] - 21 - CXA3685ER Application Circuit 3.3V 3.3V 15p 1000p 0.68 1000p 1000p 56k 3.3k NeoCapacitor: PSLA0J226M VT 36 OSCGND 35 ABS 34 CP 33 DGND 32 DVCC 31 REFVCC 30 REFGND 29 XTI 28 REFIN 27 XTO 26 NC 25 REFOUT 24 1 ADR 23 1000p 37 OSCREG NeoCapacitor 22 1000p 38 OSCVCC 39 TEST_EN 10 40 TEST_CL 41 TEST_DA 68k 16MHz X'tal 10 10 15p REFOUT 3.3V SCL 22 200 27p SDA 21 200 DGND2 20 27p 10 SCL I2C BUS SDA 42 TEST_VF PLLREG 19 1000p 43 ISOGND AGND 18 44 RFGND IOUT 17 1 IOUT 45 RFINX 47p RFIN 3.3V 47p 100p 47 RFVCC 9 REFCLOCK 10 6 MACONT 4 RACONT EACONT 5 MAOUT 3 RAOUT 46 RFIN OFFSET_I 16 0.1 OFFSET_Q 15 QOUT 14 AGND 10 AVCC 13 12 NC 11 LD 1 0.1 QOUT 120k 33k 120k 15k 100k 15k 100k 33k 1 68k 33k 10 10k 8 AGND 2 PORT 7 AGC 48 EAOUT 1 1000p 10 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same - 22 - LOCK_DET AGCIN PORT 3.3V CXA3685ER Package Outline (Unit: mm) 48PIN VQFN (PLASTIC) 6.4 6.0 C 36 37 A 25 24 B 18 8. 0.9 0.1 0.05 S Thermal Die Pad 3.0 0.6 0.1 0.7 0.4 x4 0.1 S A-B C x4 0.1 S A-B C S C 1 12 0. 6 2.2 0.03 0.03(1) (Stand Off) Solder Plating 0.13 0.025 + 0.09 0.14 - 0.03 NOTE: 1)The dimension of ( 1) is apply to DiePad and the lead. TERMINAL SECTION PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE VQFN-48P-02 P-VQFN48-6.0X6.0-0.4 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.1g LEAD PLATING SPECIFICATIONS ITEM LEAD MATERIAL SOLDER COMPOSITION PLATING THICKNESS SPEC. COPPER ALLOY Sn-Bi Bi:1-4wt% 5-18m - 23 - 0.2 0.01 0.05 M S A-B C Sony Corporation 0.225 0.03 (0 (0 .3 9) .1 5) 48 13 45 4- R 0. 3 |
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